[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
brilliant, just saw this, Cesar.  confirmed that it is functional.

commit 260625df9309f8f35541207cab431dd8dba90c5a
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Sat May 23 19:52:08 2020 -0300

    Add a few test cases with zero_a set, in combination with imm_ok


so the next one is: we need something that's a bit more sophisticated,
designed more along the lines of test_inout_mux_pipe.py:

https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/test/test_inout_mux_pipe.py;h=03fddde0f7ab12ec9023fc57b913442ba42c120a;hb=HEAD#l52

not quite that sophisticated, but close.

basically, we need:

* one function (similar to TestInput.send) which takes care of *one*
  REQ_READ and GO_RD signalling bit.  it should monitor:
  self.rd.req[N], then set self.rd.go[N] for *one* cycle (one blank yield)
  then set it self.rd.go[N] back to zero and confirm (assert) that
  self.rd.req[N] has gone to zero

* another function (similar again to TestInput.rcv) which does the same
  thing for REQ_WRITE and GO_WRITE.

* another function - a very simple one - which sets issue_i
  for one cycle (yield in between), then waits for "self.busy" to drop to 0

we can make it more sophisticated as we go along.

it should be... only... about... 80 lines of code, at a guess.

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