[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cesar i created a common function for both zero a and imm b muxing.  should be
functionally the same.

note that the Mux will automatically have its inputs extended with zero padding
to the max operand width.

so i replaced Const 0 with just 0

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