[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 16 21:07:36 BST 2020


--- Comment #12 from Michael Nolan <mtnolan2640 at gmail.com> ---
# NOTE: we really should be doing the field decoding which
# selects which bits of CR are to be read / written, back in the
# decoder / insn-isue, have both self.i.cr and self.o.cr
# be broken down into 4-bit-wide "registers", with their
# own "Register File" (indexed by bt, ba and bb),
# exactly how INT regs are done (by RA, RB, RS and RT)
# however we are pushed for time so do it as *one* register.

We can do this for crand and friends, as well as mcrf, but it doesn't work for
mtcrf or mfcr because they can read or write the whole cr register

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list