[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #12 from Michael Nolan <mtnolan2640 at gmail.com> ---
# NOTE: we really should be doing the field decoding which
# selects which bits of CR are to be read / written, back in the
# decoder / insn-isue, have both self.i.cr and self.o.cr
# be broken down into 4-bit-wide "registers", with their
# own "Register File" (indexed by bt, ba and bb),
# exactly how INT regs are done (by RA, RB, RS and RT)
# however we are pushed for time so do it as *one* register.

We can do this for crand and friends, as well as mcrf, but it doesn't work for
mtcrf or mfcr because they can read or write the whole cr register

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