[libre-riscv-dev] daily kan-ban update 12may2020

Tobias Platen libre-soc at platen-software.de
Tue May 12 15:00:08 BST 2020

On Tue, 12 May 2020 11:45:22 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

Today I began reading the code that michael had written. 
Tomorrow I will also have a short look into the PowerISA 3.1 spec. 

> yesterday i pitched in with some commentary and review on the ALU side
> of the ALU that michael is doing.  we need to back-reverse-engineer
> some implicit "well-known-in-the-industry" architectural design
> decisions related to how ALUs are fed immediates and register data
> (RA, RB, RC/RS), so as not to overwhelm the design with wires.  it's
> looking like the "RB" port by general long-standing convention is also
> the "immediate data" port.
> also i did a small commentary on the Libre-SOC article being written
> by MarketNext, sigh they are used to using google docs, so we go with
> that before moving to the wiki.  i also heard from roberto
> (powerpc-notebook) he has done an interview with charbax and wondered
> if we would like an introduction
> https://www.youtube.com/watch?v=7kM2zqTEHa8
> today i am going to start tying in the new LDSTCompUnit (currently
> going "busy" and staying there) and it will be the first time to try
> two simultaneous LDs (or STs).  i also crystallised some of the
> waffling i did yesterday on bug #305 (ALU) after analysing the forms
> for fixedshift and fixedarith, realised it might be worth considering
> to split out shift into its own ALU.
> l.
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Tobias Platen <libre-soc[at]platen-software[dot]de>

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