[libre-riscv-dev] daily kan-ban update 12may2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue May 12 11:45:22 BST 2020

yesterday i pitched in with some commentary and review on the ALU side
of the ALU that michael is doing.  we need to back-reverse-engineer
some implicit "well-known-in-the-industry" architectural design
decisions related to how ALUs are fed immediates and register data
(RA, RB, RC/RS), so as not to overwhelm the design with wires.  it's
looking like the "RB" port by general long-standing convention is also
the "immediate data" port.

also i did a small commentary on the Libre-SOC article being written
by MarketNext, sigh they are used to using google docs, so we go with
that before moving to the wiki.  i also heard from roberto
(powerpc-notebook) he has done an interview with charbax and wondered
if we would like an introduction

today i am going to start tying in the new LDSTCompUnit (currently
going "busy" and staying there) and it will be the first time to try
two simultaneous LDs (or STs).  i also crystallised some of the
waffling i did yesterday on bug #305 (ALU) after analysing the forms
for fixedshift and fixedarith, realised it might be worth considering
to split out shift into its own ALU.


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