[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 16 19:42:35 BST 2020


--- Comment #8 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)

> clueless.  suggest to use nmutil PriorityPicker on FXM (see nmutil) because
> it
> can be used do the one-hot detection very efficiently.
> if the output is not exactly equal to the input from a PriorityPicker
> (and is not zero) then this is the condition for detection that FXM
> is one-hot.
> p = PriorityPicker
> p.i.eq(FXM)
> is_onehot.eq(p.i == p.o & p.i != 0)

For mtocrf I don't think this is necessary. If the onehot condition is not
satisfied, it lists the result as being undefined. This should mean that the
current behavior is acceptable

For mfocrf, the situation is similar, the extra bits of the output register are
undefined, unless the input is onehot, in which case they are set to 0. Setting
them to 0 for all bits not selected by the mask should be acceptable here too

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list