[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)

sorry:

p = PriorityPicker(8)
comb += p.i.eq(FXM)
comb += is_onehot.eq(p.i == p.o & p.i != 0)

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