[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 20 23:14:26 BST 2020


--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
conversation notes from Tim (Raptor Engineering)


* 2x SPI master
* 4x I2C master
* 2x UART
* 4x LPC master
* EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are
PC>PCIe>OpenPower mappings

Quad SPI raptorengineering
LPC bridge github raptorengineering

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