[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 20 12:35:07 BST 2020


--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)
> discovered that there are already quite a few protocols that are much more
> widely used than omnixtend that support cache coherent memory access over a
> network: google "rdma cache coherent"

adding "wishbone" to that and opensparc T1 comes up

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