[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #13 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> (In reply to Jacob Lifshay from comment #11)
> > discovered that there are already quite a few protocols that are much more
> > widely used than omnixtend that support cache coherent memory access over a
> > network: google "rdma cache coherent"
> 
> adding "wishbone" to that and opensparc T1 comes up
> https://www.oracle.com/technetwork/systems/opensparc/opensparc-internals-
book-1500271.pdf

neat! note that wishbone is not designed to run over ethernet or similar,
unlike most other rdma protocols.

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