[libre-riscv-dev] Introduction and Questions

[Jeremy Singher]

Hi all,

My name is Jeremy Singher. I'm a graduate student studying computer
architecture, interested in open-source hardware and high performance
microarchitectures. I am looking for an open-source hardware project I can
contribute to through the course of my graduate studies, and I have some
questions about the Libre-SOC project.

1. It seems like you guys are building various components of an
out-of-order microarchitecture, such as the scoreboard, and load-store
ordering units. Do you have a complete microarchitecture diagram of the
core (or a text description)? I could find bits and pieces on specific
components, but I'm interested in details like pipeline width, depth,
branch-to-branch latency, load-use delay, etc.
2. Is the SoC at a state at which I can evaluate performance on simple
benchmarks in simulation? Other similar open-source hardware projects have
make targets to launch verilator simulations, but I could not find an
equivalent in your repos (although I probably am just bad at looking).
3. What is your target performance in terms of an established benchmark
like Coremark, Dhrystone, Embench, or SPEC? I'm trying to compare the
merits and progress of various hardware projects out-there.
4. What is the right way to get started contributing? My experience is with
Verilog, and I've looked at other languages too, including BSV and Chisel.
I'm primarily interested in developing microarchitecture for
performance-critical components, like branch predictors, prefetchers,
instruction schedulers, and load-store units. Ideally, I could contribute
my work as part of graduate studies to this project.

Sorry for the barrage of questions.

Best,
-Jeremy