[libre-riscv-dev] daily kan-ban update 13may2020
libre-soc at platen-software.de
Wed May 13 14:56:47 BST 2020
On Wed, 13 May 2020 11:28:25 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> yesterday i started on integrating the LDSTCompUnit into the
> scoreboard and immediately ran into a brick wall in the form of the
> address-request/release signalling. when go_addr is raised (in
> response to req_addr), the LDSTCompUnit is supposed to drop req_addr
> one cycle later: instead it stays high.
> i also investigated microwatt to find out what the heck is going on
> with the register-order-swapping. turns out that different classes of
> operations (logical, rotate, arith) have different ordering. why? who
> today i will continue working through the address-negotiation in LDSTCompUnit.
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
I've looked into the soc/src/soc/decoder/isa and src/soc/alu/ directories.
There is a TODO that references the PowerISA PDF, so I will first read the
following sections, before writing anything.
# 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
# note that mffs, mcrfs, mtfsf "manage" this FPSCR
# 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
# note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
# 2.3.2 LR (actually SPR #8)
# 2.3.3 CTR (actually SPR #9)
# 2.3.4 TAR (actually SPR #815)
# 3.2.2 p45 XER (actually SPR #0)
# 3.2.3 p46 p232 VRSAVE (actually SPR #256)
I assume that that the version of the pdf referenced is still 3.0 one and not 3.1 recently released.
Tobias Platen <libre-soc[at]platen-software[dot]de>
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