[libre-riscv-dev] Introduction and Questions
programmerjake at gmail.com
Fri May 15 22:19:48 BST 2020
On Fri, May 15, 2020, 13:50 Jeremy Singher <thejsingher at gmail.com> wrote:
> > the DIV pipeline will be... 8 (maybe more), MUL will be 2, ADD (etc.)
> will be 1.
> > * fetch: 1.
> > * decode: 1.
> > * issue and reg-read: 1 (minimum).
> > * execute: between 1 and 8 (maybe more)
> > * write: 1 (minimum)
> So this is just for the preliminary tapeout? I would expect an OOO
> core targeting 1GHz+ to have more pipeline stages than this (10+). The
> A72, Skylake, Zen, and BOOM all seem to target 10+ stages.
We will definitely need more stages in the fetch pipeline for branch
prediction, TLB, and cache handling, I'm guessing 2 or 3 fetch stages.
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