[libre-riscv-dev] [Bug 316] bperm TODO

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 16 22:15:12 BST 2020


--- Comment #16 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> i've put a stack of TODO comments in for you.  always remember to "git pull"
> before doing any editing.  keep people informed what you are doing,
> "i am going to edit this file, now" for example, because this will help you
> to avoid edit-conflicts (because the other person knows to coordinate with
> you).
> for example, if you had fixed the thing in the previous comment *without*
> a "git pull", committed it, *then* tried "git pull" you would now have
> a conflict to resolve, because you edited the exact same line that i had
> also edited.
> we will soon see if you are checking the bugtracker and reading all
> comments... :)

Thank you for the very helpful TODOs Luke. I think I've made the necessary
changes, and the graph looked quite different as a made each change. Especially
the first one, as prior to that as you had noted I had neglected to 'connect' a
key component.

 for i,n in enumerate(signals):
-    n.eq(self.rb[i])
+    m.d.comb += n.eq(self.rb[i])

I have committed the changes. Now I am going to go over Robert Baruch's nmigen
tutorials and search out resources on writing unit tests, and formal proofs for
hardware. Then I will attempt to write an appropriate unit test for this class.

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