[libre-riscv-dev] Introduction and Questions
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat May 16 22:42:35 BST 2020
On Sat, May 16, 2020 at 9:34 PM Jeremy Singher <thejsingher at gmail.com> wrote:
> > Ok after some reflection I do see the most possible performance
> > difference in procedures calls. Most of the time in procedures some
> > scratch registers are pushed on the stack at entering.
> Its actually a performance difference on more cases than this. In the
> case of W R W R sequence to the same register, the second Write should
> be allowed to proceed before the first Write is executed, which also
> unblocks the second R.
in a strict historically-accurate 6600 (which we are not doing), it would block
at that 2nd W.
in the precise-augmented 6600-like design, the Operand Forwarding Bus
would provide the means for the second W to communicate the required
result to the 2nd R, allowing it to proceed, because Operand Forwarding
Buses provide the extra missing path that is not in the *original* 6600
that makes the register data paths functionally identical to a Common
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