[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #10 from Michael Nolan <mtnolan2640 at gmail.com> ---
Does it make sense to have the ALU inputs a and b be PartitionedSignals?

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