[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=306

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmm

the same thing we noted in Branch, for CMPEQB is also not being picked up n the
main_stage.py

https://libre-soc.org/openpower/isa/comparefixed/

cmpeqb is only supposed to alter the CR, not the main register RT.

the formal proof is not picking that up.

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