[libre-riscv-dev] minimum viable ASIC

Yehowshua yimmanuel3 at gatech.edu
Fri May 8 13:50:12 BST 2020

But really guys, I’m betting the Series A will be just fine, from it, we can hire some talented engineers, and from then on, execution, not finances will be our bottleneck.

What I really need is an “hello world” on FPGA by demo day for August.


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