[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #81 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Created attachment 61
  --> https://bugs.libre-soc.org/attachment.cgi?id=61&action=edit
ALU main stage

hilarious.  the actual OP_ADD, OP_CMPEQB, OP_CMP and OP_EXTS operations
are ridiculously small compared to the support infrastructure: regfile,
DMs, everything basically.

i'd heard that routing of data is by far and above the majority of
a CPU: it's kind-of illuminating to actually see how small an ALU
can be.

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