[libre-riscv-dev] note on memory operation requirements for linux

Jacob Lifshay programmerjake at gmail.com
Fri May 8 20:15:25 BST 2020

I haven't checked but I'm 99% sure that we will need to implement standard
Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
and non-cacheable load/store operations if we want to support Linux on our
october test chip.


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