[libre-riscv-dev] note on memory operation requirements for linux

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 9 00:11:26 BST 2020

On Fri, May 8, 2020 at 8:15 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> I haven't checked but I'm 99% sure that we will need to implement standard
> Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
> and non-cacheable load/store operations if we want to support Linux on our
> october test chip.

added  to page.  good catch.

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