[libre-riscv-dev] note on memory operation requirements for linux
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed May 13 19:41:14 BST 2020
On Sat, May 9, 2020 at 12:11 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Fri, May 8, 2020 at 8:15 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> > I haven't checked but I'm 99% sure that we will need to implement standard
> > Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
> > and non-cacheable load/store operations if we want to support Linux on our
> > october test chip.
> added to page. good catch.
3.1B (POWER10) doc says that atomics and so on are optional. this is
good, although performance would suck.
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