[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/virtual_port.py;hb=HEAD

i think i have it.  i had to modify RegFileArray to first get it to give me
only (an array of) read/write ports to each (small) register.

however... *this is not the full story*!

we need to prevent and prohibit RegFileArray.read_port() and
RegFileArray.write_port() from having a "bypass" on the registers

this is complicated.

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