[libre-riscv-dev] [Bug 299] New: improve memory clash detection

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 2 00:39:59 BST 2020


            Bug ID: 299
           Summary: improve memory clash detection
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---


see this message (and the one before it).

must work through to see if there is a way to combine the Mem Hazard Matrix
logic with addr match and spot interleaved LDs and STs that do not clash.

at the moment, *any* LD will stop future STs from going through.  *any* ST
likewise stops LDs from going through.

it *may* be possible to use addr match on LSBs to determine which interleaved
LDs and STs can be separated into batches of LDs and batches of STs.

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