[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl

line 563 is where sraw, srad, srawi and sradi exist.  there's a *lot*
of code-duplication, which is fairly normal in "traditional" HDLs because
parameterisation can be harder to do.

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