[libre-riscv-dev] more compatible alternative to BE instructions on LE processor

Jacob Lifshay programmerjake at gmail.com
Wed May 13 03:56:45 BST 2020

Since having the instruction stream be BE is not directly compatible with
existing LE instructions since calling between them requires a mode switch
to switch endian, I propose a different solution that doesn't require any
mode switch, is compatible with LE instructions, and allows supporting
instructions that are any size, though will probably be limited to
multiples of 16 bits.

My idea is to switch the logical order that instructions are decoded such
that decoding 32-bit LE words starts with the most-significant byte which
contains the opcode, instead of the least-significant byte.

PC would effectively be split into two fields, where the top N-2 bits are
the address like usual, but the bottom 2 bits instead address memory in
reversed order:

PC value -> memory address
0x1000 -> 0x1003
0x1001 -> 0x1002
0x1002 -> 0x1001
0x1003 -> 0x1000
0x1004 -> 0x1007
0x1005 -> 0x1006
0x1006 -> 0x1005
0x1007 -> 0x1004
0x1008 -> 0x100B
0x1009 -> 0x100A
0x100A -> 0x1009
0x100B -> 0x1008
0x100C -> 0x100F
0x100D -> 0x100E
0x100E -> 0x100D
0x100F -> 0x100C
0x1010 -> 0x1013

Since all currently existing Power instructions are a multiple of 32 bits,
this wouldn't change how they are decoded or executed, however, would
change how new 16 or 48-bit instructions are laid out.

If the processor is switched to BE mode (for both instructions and data),
this address reordering would be disabled, since BE mode already has the
opcode byte as the first byte anyway.

(PDP endian resurrected -- sort of)


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