[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #80 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/isa/comparefixed/

hmm hmmm the cmpeqb code is stopping ALUIntermediateData from not having cr0 in
it.

i suggest instead that we put the 8 bits into self.o.o, then special case
cmpeqb to test o.any() and only set cr0[2]

also hmm, cmp* seem to want to store the comparison in a BR indexed register,
not cr0.

which sigh tends to suggest we need to move cmp operations to their own
pipeline, one that takes the full 32 bits of CR.

alternatives are that we expand ALU cr to the full bit width.

however if going that route i would like to suggest we pass an index (and mask)
saying which CR(s) have been modified.

the mask would be sent as write enable lines to the CR regfile.

this would remove the need to pass *in* the full CR and stop an unnecessary
read hazaelrd being created.

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