[libre-riscv-dev] daily kan-ban update 25may2020
colepoirier at gmail.com
Tue May 26 00:22:35 BST 2020
May 25 2020, at 3:45 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> we need to find the full implementation, an actual serialized-irq master
After about 30 min of googling I've only been able to find the following
which I believe from the below copyright is what you're looking for?
$Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
//// serirq_host.v - SERIRQ Host Controller ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/wb_lpc/ ////
//// Author: ////
//// - Howard M. Harte (hharte at opencores.org)
Once you let me know if this is correct I'll add it to the wiki and
crossref with bug 304.
Aside from this, my only other active bug report is to do with fixing
one small thing in coriolis2 chroot setup script and documenting the
changes to the hdl_workflow on the wiki. Is there HDL work that I can
take on? Possibly some formal proofs that I could see if I can crack?
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