[libre-riscv-dev] PowerISA 3.1 (Power10) spec released

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue May 12 08:36:13 BST 2020

On Tue, May 12, 2020 at 7:00 AM Lauri Kasanen <cand at gmx.com> wrote:
> Hi,
> The thing that stood out to me in the levels was BE/LE. An int or float
> compatible Power processor must support BE, LE is optional at those
> levels. A Linux level processor must support LE, BE is optional at that
> level. However the Linux level requires SIMD.
> So this means that our int+float processor must support BE.

michael and i have added BE byte-flipping into the instruction decode,
which is code used by both the simulator and the hardware.

we need BE because without it we cannot detect Compressed, VBLOCK or
SVPrefix modes in the same instruction stream as 32-bit operations,
because only in BE mode will the opcode be in the front 2 bytes in the
sequential bytes read from the instruction stream.

see https://libre-soc.org/openpower/

where it is mentioned that we will need to take 8 major opcodes to do
this: 2 bits per "mode".


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