[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i'm not seeing anything in main_stage.py that uses XER carry_in.  it appears
extraneous.  sticky overflow on the other hand, because carry can be generated,
should be.

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