[libre-riscv-dev] [Bug 325] New: create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

            Bug ID: 325
           Summary: create POWER9 TRAP pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

we need a "trap" pipeline, or to decide if this is to be considered part of
Branch, due to the changes that trap makes to the PC.  this by analysing the
register port allocation.

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