[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #32)
> (In reply to Cesar Strauss from comment #31)
> > Regarding the parallel test:
> > 
> > Pushed a proof of concept.
> > 
> > Defective as it was, I pushed it anyway, hoping for some feedback on the
> > bug. Found it myself literally seconds after pushing.
> 
> :)
> 
> ok i added some stubs here.

right.  so i've pushed another commit which shows where we would expect to
put the inputs in (constructor).  rather than have them directly as arguments
to op_sim(), all those arguments - a, b, op, inv_a, imm_ok, zero_a - they
become the arguments to the constructor.

also expected_o should be in the constructor as well.

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