[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jacob i've added documentation of the requirements of PortInterface:
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=6404cf302734700514e7553bdf6c5a5df5badeb8

i'm doing a "dummy" one at the moment which will implement this API,
only allowing the one (and only one) Memory read/write per cycle.
this makes it clear exactly where the "merging" needs to take place.

putting the (twin/quad) L1 Caches in place once the L0CacheBuffer
has a single-cycle 128-bit-wide interface should be dead straightforward.

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