[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 4 11:21:30 BST 2020


--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jacob i've added documentation of the requirements of PortInterface:

i'm doing a "dummy" one at the moment which will implement this API,
only allowing the one (and only one) Memory read/write per cycle.
this makes it clear exactly where the "merging" needs to take place.

putting the (twin/quad) L1 Caches in place once the L0CacheBuffer
has a single-cycle 128-bit-wide interface should be dead straightforward.

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