[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i looked more closely at the difference between branch, sys and trap, and rheir
combination would be a massive EIGHT incoming register ports.

* RA, RB, CR, MSR for trap
* 2x SPRs, MSR for syscalls
* 2x SPRs, no MSR for branches

this is too much.

i had assumed that MSR was a SPR, it isn't.

so the number of SPRs for branch can be reduced to 2.  spr3 can be deleted.

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