[libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 18 12:29:45 BST 2020


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
dang.  these XER bits really do need to be treated as individual registers
covered by separate DM rows.

if we don't they'll chain together and completely destroy any opportunity
for parallelism.

this in turn means we need to define a function which, rather laboriously,
tells us at the instruction *decode* phase, what implicit "registers"
(which fields) are to be written to, and which to be read/write.  SO is
definitely on that list.

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