[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #5 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Michael Nolan from comment #3)

> 
> yes, with an "op" - which in our case will basically be "decoder.InternalOp"
> 

> 
> damnit this needs to be on the bugreport, i haven't got time, 10m until
> meeting
> 
> see page 8, diagram at the top.
> 
> Those 4 batches of Function Units are *completely separate*.  they do
> *NOT* interact.
Oh ok. So essentially we will have *separate* ports for the addition pipe, the
multiplication pipe, the branch pipe, and instructions can be issued to each in
parallel. 


> actually you know what, screw it: make separate ones for MUL and DIV,
> pretty much exactly like in that diagram on p8.  we're doing a
> radically different design as a proof-of-concept.
> 
> * add sub neg compare logical shift all go in their own
> Reservation-Station-style FunctionUnit
> * MUL in its own separate RS/FU
> * DIV likewise
yeah looks like it

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