[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 8 16:35:47 BST 2020


--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

will need to pass in everything and pass out everything.  carry-in as
well as carry-out.

the pipelines have to take *everything* that they need to produce a
result: they are not permitted to access global resources such as

this is why we have different FunctionUnits with totally different
specs() because for Branch it will take CTR and LR *as input*, where
for ALU it will take CR0 and a and b and so on

and for the MUL FU it will take about *four* possibly 5 inputs:
RA RB RC (for MAC) *and* carry-in *and* CR0 etc. etc.

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