[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #71 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #70)
> (In reply to Luke Kenneth Casson Leighton from comment #68)
> >   File "/home/lkcl/src/libresoc/soc/src/soc/decoder/isa/fixedlogical.py",
> > line 223, in op_prtyd
> >     s = s / RS[i % 8 + 7]
> > 
> > erm... ermermerm... that doesn't look right.  divide?  instead of ^ (XOR)?

> There's no way they actually mean division there... If so, then every time
> that bit is 0 you get a divide by 0...

yep it's a manual transcription error from when i extracted the text from the
PDF.  i've git pushed ^ instead of /, done the submodule update too.

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