[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #72 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #68)
>   File "/home/lkcl/src/libresoc/soc/src/soc/decoder/isa/fixedlogical.py",
> line 223, in op_prtyd
>     s = s / RS[i % 8 + 7]
> 
> erm... ermermerm... that doesn't look right.  divide?  instead of ^ (XOR)?
> 
> TypeError: unsupported operand type(s) for /: 'int' and 'SelectableInt'
> 

The modulus doesn't fit with the description of what the instruction does or
with the behavior on qemu. I think they meant for that to be a multiplication.

Should we report this to IBM? It looks like they corrected the xor part in the
3.1 spec, but they're still using modulus for the bit indices.

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