[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #73 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is from V3.0B - page 98:

s <- 0
t <- 0
do i = 0 to 3
   s <- s / (RS)[i%8+7]
do i = 4 to 7
   t <- t / (RS)[i%8+7]

so yes that's wrong (divide).


microwatt ppc_fx_insns.vhdl has this:

    function ppc_prtyd (rs: std_ulogic_vector(63 downto 0)) return
std_ulogic_vector is
        variable tmp : std_ulogic;
        variable ret : std_ulogic_vector(63 downto 0);
    begin
        ret := (others => '0');

        tmp := '0';
        for i in 0 to 7 loop
            tmp := tmp xor rs(i*8);
        end loop;

        ret(0) := tmp;
        return ret;
    end;

and that's definitely "times 8" there.

note that they didn't end up using that function, the loop was unrolled as
follows:

        par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
        par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);

so yes, please do correct the pseudo-code and report it as a bug in
the spec to IBM (good idea to cross-reference this discussion)

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