[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #79 from Cole Poirier <colepoirier at gmail.com> ---
Unfortunately I think I have reached a blocker. When attempting to run the
tests, I get to testing the test_rand_imm_logical():
```
['ori 3, 1, 18936']
['xori 3, 1, 18465']
```

Then I get this error which I don't think I am able to fix.
```
['xori 3, 1, 18465']
.
----------------------------------------------------------------------
Ran 9 tests in 3.111s

OK
ControlBase <soc.fu.logical.pipeline.LogicalBasePipe object at 0x7fbf8d70ea20>
None None False
DynamicPipe init <super: <class 'DynamicPipe'>, <LogicalStages object>>
(<soc.fu.logical.pipe_data.LogicalPipeSpec object at 0x7fbf8d70e908>,)
redir <abc.LogicalStages object at 0x7fbf8d70e6a0>
(<soc.fu.logical.pipe_data.LogicalPipeSpec object at 0x7fbf8d70e908>,)
ControlBase <abc.LogicalStages object at 0x7fbf8d70e6a0> <abc.LogicalStages
object at 0x7fbf8d70e6a0> None False
E
======================================================================
ERROR: run_all (__main__.TestRunner)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "test_pipe_caller.py", line 201, in run_all
    sim = Simulator(m)
  File "/home/colepoirier/src/nmigen/nmigen/back/pysim.py", line 933, in
__init__
    self._fragment = Fragment.get(fragment, platform=None).prepare()
  File "/home/colepoirier/src/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/colepoirier/src/nmigen/nmigen/hdl/dsl.py", line 537, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name],
platform), name)
  File "/home/colepoirier/src/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/colepoirier/src/nmigen/nmigen/hdl/dsl.py", line 537, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name],
platform), name)
  File "/home/colepoirier/src/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/colepoirier/src/soc/src/soc/decoder/power_decoder.py", line 328,
in elaborate
    m = PowerDecoder.elaborate(self, platform)
  File "/home/colepoirier/src/soc/src/soc/decoder/power_decoder.py", line 275,
in elaborate
    comb += self.op._eq(row)
  File "/home/colepoirier/src/soc/src/soc/decoder/power_decoder.py", line 152,
in _eq
    self.cr_out.eq(CROutSel[row['CR out']]),
  File "/usr/lib/python3.7/enum.py", line 352, in __getitem__
    return cls._member_map_[name]
KeyError: '0'
```

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