[libre-riscv-dev] daily kan-ban update 27may2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed May 27 13:25:06 BST 2020
* altered VirtualRegPort to simplify it and got a proof of concept unit
test, enough to be happy to move on
* added CR and XER regfiles (using VirtualRegPort) and also a Fast Regfile
(PC, LR, CTR, MSR). the Fast regfile is going to be a handful. 3R3W (maybe
more), no way we can use SRAMs.
* reviewed Tobias's DataMerger class. principle looks good.
* answered Cole about regfile proofs. we work on them together.
* reviewed Systemes Libre Company.
* collaborate with Cole with regfile proofs
* help Cesar with parallel compunit test
* read proof_fu.py again
* do a unit test similar to test_pipe_caller.py which uses MultiCompUnit
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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