[libre-riscv-dev] daily kan-ban update 27may2020
colepoirier at gmail.com
Wed May 27 17:35:04 BST 2020
Studied virtual_port.py to understand nmigen, hdl, and hardware better
because its the full implementation of something I tried to implement
but really struggled to understand. Being able to compare my effort on
this to the end product is nearly as helpful to my learning as was the
tremendous amount of help Michael and Luke provided working through
writing bpermd.py and proof_bpermd.py. Thank you.
I also started working through the very basic first assertions for the
formal proof of Register, RegFile, and RegFileArray from
regfile/regfile.py, which I will work on with Luke today.
More information about the libre-riscv-dev