[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 14 20:10:19 BST 2020


--- Comment #68 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
  File "/home/lkcl/src/libresoc/soc/src/soc/decoder/isa/fixedlogical.py", line
223, in op_prtyd
    s = s / RS[i % 8 + 7]

erm... ermermerm... that doesn't look right.  divide?  instead of ^ (XOR)?

TypeError: unsupported operand type(s) for /: 'int' and 'SelectableInt'

i think, really, we need to do the same trick done with eq, ge etc, turn all
operations from using python "op1 + op2" into "add(op1, op2)" and sort out
the operands - convert to SelectableInt - in there.

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