[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #69 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #67)
> (In reply to Luke Kenneth Casson Leighton from comment #66)
> 
> > i added popcount (because).  it looks like it works except test_cmpb is
> > not working
> 
> after updating submodules (will commit in a sec)
> 
>   File "/home/lkcl/src/libresoc/soc/src/soc/decoder/isa/fixedlogical.py",
> line 193, in op_cmpb
>     if eq(RS[8 * n:8 * n + 7 + 1], RB[8 * n:8 * n + 7 + 1]):
> NameError: name 'RS' is not defined

Oops, needed a patch (or figuring out why the compiler didn't include RS)

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