[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #1)
> Are we planning to do crand, cror, crxor, and friends? They're not
> implemented in microwatt as far as I can tell

https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl
line 719.

oink.

am i reading this correctly: they actually use the cr operand as if
it was a *table*??  moo?

so the instruction field 0-15 is treated as a 4-bit number (a 4-bit
truth-table)

you then take ba and bb and create a 2-bit index.

then use that 2-bit address to get one of the bits of the 4-bit
instruction field.

wooow.

i'm deeply impressed.

um... answer... yes they do implement crand, cror etc :)

this must be how FPGAs do things, and is probably why LUTs are 4-bit.

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