[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #3 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> michael i am just reviewing the isatables for LOGICAL operations.  two
> things struck me:
> 
> 1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no
> cr0 in LogicalInputData.

That's a mistake, fixing...

> 
> 2. i am not seeing any of the LOGICAL operations listed as needing carry in
> nor producing carry out.
> 
> looking here:
> https://libre-soc.org/openpower/isa/fixedlogical/
> 
> it does not appear that any or them set anything other than CR0 and that is
> an output only.

They shouldn't need carry no. 

BTW, did the logical pipe's output stage get replaced with common_output_stage?
The logical pipe test is broken and I'm not sure how to fix it.

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