[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> could also add SPRSET as well (1 more SPR reg to input)

no, it's 2.  too many.  2 because one is FAST (covering TAR, LR, SRR0/1 etc.)
the other is for the (slow) SPR regfile SRAM.  not a good idea.  that's 6
input regs, and 6 output.

-- 
You are receiving this mail because:
You are on the CC list for the bug.