[libre-riscv-dev] [Bug 296] New: idea: cyclic buffer between FUs and register file

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=296

            Bug ID: 296
           Summary: idea: cyclic buffer between FUs and register file
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

the issue that we have is that multiplexing between a dozen FUs with multiple
read/write ports, and the available regfile read/write ports, does not quite
match up.  full crossbars are completely impractical.

we therefore need something that allows FUs to receive / send values, without
a complete overload of wiring or muxes.

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