[libre-riscv-dev] minimum viable ASIC

[Luke Kenneth Casson Leighton]

On Fri, May 8, 2020 at 1:44 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:

> I talked to Raptor and if Series A doesn’t pan out in August, Raptor is willing to foot 30k for PLL design in exchange for some equity.

that's fantastic.  it would give us (and any other team)
Foundry-independence.  normally the PLL is available as a Standard
Cell from a Foundry... but only under NDA.

l.